2012Unpublished venueRequires access

Design of CMOS 8-BIT Comparator for Low Power Application

Sanjay Kumar Jaiswal, Kumkum Verma, Gyanendra Kumar Singh, Neeraj Pratihar

Open publisher page 10 citations

Abstract

In this paper we have presented two different designs for 8-bit comparator, one is conventional comparator and other is low power comparator. First of all we have designed conventional comparator and using this 8 bit comparator is implemented. The circuit produces 2 output X and Y. X is active when A>;B, X is not active when A<;B or A=B. Y is active when A=B, otherwise not active. Our approaches is first to design 1- bit comparator as one component and then generate its symbol to design 8-bit comparator. From the given comparison table we see that power and area is reduced upto 73% and 23.25% in low power comparator in comparison with conventional comparator. All the simulations are performed using tanner and Microwind software at TSMC 120nm technology.

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What this paper is about

In this paper we have presented two different designs for 8-bit comparator, one is conventional comparator and other is low power comparator. First of all we have designed conventional comparator and using this 8 bit comparator is implemented. The circuit produces 2 output X and Y. X is active when A>;B, X is not active when A<;B or A=B. Y is active when A=B, otherwise not active. Our approaches is first to design 1- bit comparator as one component and then generate its symbol to design 8-bit comparator. From the given comparison table we see that power and area is reduced upto 73% and 23.25% in low power comparator in comparison with conventional comparator. All the simulations are performed using tanner and Microwind software at TSMC 120nm technology.

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Available abstract

In this paper we have presented two different designs for 8-bit comparator, one is conventional comparator and other is low power comparator. First of all we have designed conventional comparator and using this 8 bit comparator is implemented. The circuit produces 2 output X and Y. X is active when A>;B, X is not active when A<;B or A=B. Y is active when A=B, otherwise not active. Our approaches is first to design 1- bit comparator as one component and then generate its symbol to design 8-bit comparator. From the given comparison table we see that power and area is reduced upto 73% and 23.25% in low power comparator in comparison with conventional comparator. All the simulations are performed using tanner and Microwind software at TSMC 120nm technology.

Key concepts: Comparator, Comparator applications, CMOS, Computer science, Bit (key), Power (physics), Electronic engineering, Electrical engineering

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