Single flux quantum counting sinc filter with multistage decimation structure

We have been developing a third-order sinc decimation filter in order to realize an oversampling sigma delta A/D converter with a second-order modulator. The sinc filter is formed from a multistage decimation structure, which is suitable for a high-speed operation. A 4-bit destructive readout (DRO) counter, which was an elementary circuit of the sinc filter and was also utilized as a first-order sinc filter with a decimation factor of 8, was designed and its proper operation was confirmed with a dc bias current margin of ±33% from a low-frequency measurement. The 4-bit DRO counter also operated up to the data rate of 4.8 Gbps with a dc bias current margin of ±29% from a high-frequency measurement. The third-order sinc filter with a decimation factor of 2, which was an elementary circuit block of our multistage decimation third-order sinc filter, was designed and its proper operation was confirmed from a low-frequency measurement. The third-order sinc filter with a decimation factor of 2 consisted of a 3-bit shift register, three 2-bit DRO counters and a 4-bit DRO counter, containing 441 junctions, and its power consumption was estimated to be 59 μW. This paper was presented at the 8th International Superconductive Electronics Conference, Osaka, Japan, 19–22 June 2001.