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1981•IEEE Journal of Solid-State CircuitsRequires access

A highly sensitive strobed comparator

A. Yukawa

Open publisher page 4 citations

Abstract

A sensitive strobed comparator has been designed and extensively characterized. It is realized in a standard NMOS silicon-gate process, occupying a die area of 0.05 mm/SUP 2/ (81/mil/SUP 2/). Power consumption is 1 mW from a single 10 V supply. Resolution is 0.5 mV when a strobe signal rise from 0 V to 5 V in 20 ns. Offset voltage had a mean value of -0.5 mV with a standard deviation of 5 mV. This comparator should be useful for high-resolution analog-digital converters in NMOS technology.

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What this paper is about

A sensitive strobed comparator has been designed and extensively characterized. It is realized in a standard NMOS silicon-gate process, occupying a die area of 0.05 mm/SUP 2/ (81/mil/SUP 2/). Power consumption is 1 mW from a single 10 V supply. Resolution is 0.5 mV when a strobe signal rise from 0 V to 5 V in 20 ns. Offset voltage had a mean value of -0.5 mV with a standard deviation of 5 mV. This comparator should be useful for high-resolution analog-digital converters in NMOS technology.

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OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A sensitive strobed comparator has been designed and extensively characterized. It is realized in a standard NMOS silicon-gate process, occupying a die area of 0.05 mm/SUP 2/ (81/mil/SUP 2/). Power consumption is 1 mW from a single 10 V supply. Resolution is 0.5 mV when a strobe signal rise from 0 V to 5 V in 20 ns. Offset voltage had a mean value of -0.5 mV with a standard deviation of 5 mV. This comparator should be useful for high-resolution analog-digital converters in NMOS technology.

Key concepts: Comparator, NMOS logic, Converters, Comparator applications, Offset (computer science), Voltage, Materials science, Electrical engineering

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