High speed asynchronous structures for inter-clock domain communication

This paper describes a globally asynchronous, locally dynamic system (GALDS) design paradigm. In a GALDS design, many synchronous blocks are inter-connected using dedicated asynchronous links. Each synchronous block is associated with a local clock generator and features dynamic frequency scaling in order to utilize the least possible power for the required performance to be achieved. Two different asynchronous structures are explored in this paper and they each feature high throughput, modular design and high tolerance to metastability errors that occur when communicating between clock domains. These structures utilize a 4-phase dual track asynchronous control circuit to control either a single direction FIFO with data traveling uniquely in one direction or a bidirectional FIFO that is capable of transmitting data simultaneously in both directions by precisely controlling when data has access to a common, shared datapath. These structures have been created in TSMC's CMOSP18 technology.