Trudi-Heleen Joubert, Evert Seevinck, M. du Plessis
Abstract
In CMOS, an SRAM cell containing six transistors is generally used. If a smaller number of transistors and fewer connection lines were possible, the packing density of SRAM chips may be improved. A reduce-area four-transistor SRAM cell for implementation in a standard digital CMOS process is proposed in this paper.
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In CMOS, an SRAM cell containing six transistors is generally used. If a smaller number of transistors and fewer connection lines were possible, the packing density of SRAM chips may be improved. A reduce-area four-transistor SRAM cell for implementation in a standard digital CMOS process is proposed in this paper.
Key concepts: Static random-access memory, CMOS, Transistor, Electronic engineering, Computer science, Materials science, Electrical engineering, Engineering