Effect of structure scaling on the offset levels for CMOS Hall Effect sensors

The effect of the structure scaling on the Hall Effect sensors performance (including offset values) is investigated. To this purpose, the Hall devices have been integrated in a regular bulk CMOS technology and tested for their main parameters. The comparative analysis is focused on three Hall cells (basic, L, XL), with progressive scaled up dimensions. Measurements results for the sensitivity, offset voltage and magnetic equivalent offset are included for the three considered Hall cells.