2003Unpublished venueRequires access

2.5 V-driven Nch 3rd generation trench gate MOSFET

Ai Osawa, Y. Kanemaru, Noboru Matsuda, Tomoaki Yoneda, H. Matsuki, Yuki Usui, Y. Baba

Open publisher page 9 citations

Abstract

We developed a 3rd generation trench gate MOSFET driven by a gate voltage of 2.5 V. The on-resistance (R/sub on/) of the 3rd generation device has been reduced by 40% compared with the conventional (2nd generation) device, to the value of 12 m/spl Omega/ maximum (at V/sub GS/=2.5 V) by using certain techniques. In order to reduce the R/sub on/ value, it is necessary to thin the epitaxial layer and shrink the chip size. In order to thin the epitaxial layer, it is important to control trench depth exactly to maintain the drain-source breakdown voltage (V/sub DSS/). This is done by using a trench RIE machine with an in-situ monitoring system. For shrinkage of the chip size, a narrow trench formation process and a double trench (additional contact trench) structure are applied to the 3rd generation trench gate MOSFET. Using these new techniques, we succeeded in the development of a 3rd generation trench gate MOSFET with the lowest R/sub on/ value reported to date.

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What this paper is about

We developed a 3rd generation trench gate MOSFET driven by a gate voltage of 2.5 V. The on-resistance (R/sub on/) of the 3rd generation device has been reduced by 40% compared with the conventional (2nd generation) device, to the value of 12 m/spl Omega/ maximum (at V/sub GS/=2.5 V) by using certain techniques. In order to reduce the R/sub on/ value, it is necessary to thin the epitaxial layer and shrink the chip size. In order to thin the epitaxial layer, it is important to control trench depth exactly to maintain the drain-source breakdown voltage (V/sub DSS/). This is done by using a trench RIE machine with an in-situ monitoring system. For shrinkage of the chip size, a narrow trench formation process and a double trench (additional contact trench) structure are applied to the 3rd generation trench gate MOSFET. Using these new techniques, we succeeded in the development of a 3rd generation trench gate MOSFET with the lowest R/sub on/ value reported to date.

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Available abstract

We developed a 3rd generation trench gate MOSFET driven by a gate voltage of 2.5 V. The on-resistance (R/sub on/) of the 3rd generation device has been reduced by 40% compared with the conventional (2nd generation) device, to the value of 12 m/spl Omega/ maximum (at V/sub GS/=2.5 V) by using certain techniques. In order to reduce the R/sub on/ value, it is necessary to thin the epitaxial layer and shrink the chip size. In order to thin the epitaxial layer, it is important to control trench depth exactly to maintain the drain-source breakdown voltage (V/sub DSS/). This is done by using a trench RIE machine with an in-situ monitoring system. For shrinkage of the chip size, a narrow trench formation process and a double trench (additional contact trench) structure are applied to the 3rd generation trench gate MOSFET. Using these new techniques, we succeeded in the development of a 3rd generation trench gate MOSFET with the lowest R/sub on/ value reported to date.

Key concepts: Trench, MOSFET, Materials science, Optoelectronics, Breakdown voltage, Voltage, Electrical engineering, Layer (electronics)

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