A fixed-point implementation of the expanded hyperbolic CORDIC algorithm

he original hyperbolic CORDIC (Coordinate Rotation Digital Computer) algorithm [1] imposes a limitation to the inputs ’ domain which renders the algorithm useless for certain applications in which a greater range of the function is needed. To address this problem, Hu et al [2] have proposed an interesting scheme which increments the iterations of the original hyperbolic CORDIC algorithm and allows an efficient mapping of the algorithm onto hardware. A fixed-point implementation of the hyperbolic CORDIC algorithm with the expansion scheme proposed by Hu is presented. Three architectures are proposed: a low cost iterative version, a fully pipelined version, and a bit serial iterative version. The architectures were described in VHDL, and to test the architecture, it was targeted to a Stratix FPGA. Various standard numerical formats for the inputs are analyzed for each hyperbolic function directly obtained: Sinh, Cosh, Tanh-1 and exp. For each numerical format and for each hyperbolic function an error analysis is performed.