A parallel packet switch supporting variable-length packets

In this paper, we propose demultiplexer and multiplexer algorithms in the architecture of parallel packet switches (PPS) which support variable-length packet switching. The proposed algorithms are easier to implement because the re-sequence and re-construction schemes are not needed. And the load balance of switching planes is also guaranteed. Combined with some recently proposed variable length packet scheduling algorithms, the proposed algorithms can efficiently accommodate IP traffic. The performance of the algorithms is evaluated through simulation, and the comparison with the previous work shows that the proposed algorithms are competent for variable-length packet switching.