Continuously tunable, very long time constant CMOS integrator for a neural recording implant
Robert H. Rieger, Andreas Demosthenous, John T. Taylor
Abstract
Robert H. Rieger, Andreas Demosthenous, John T. Taylor
Abstract
This paper describes the implementation of a low-power, very long time constant integrator for use in an adaptive neural recording system for implantable neuroprostheses of very low frequency continuous-time filters. The integrator is based on the OTA-C approach and a very small transconductance (g/sub m/) of 125 pA/V was achieved by cascading a short chain of g/sub m/-1/g/sub m/ stages. The time constant of the integrator is tunable between 0.8 s to 2.5 s, and any offset voltages at the output terminal may be trimmed. The circuit was fabricated in a 0.8 /spl mu/m CMOS process, dissipates 230 nW from /spl plusmn/1.5 V power supplies (excluding the bias circuitry and output buffer) and has a core area of 0.1 mm/sup 2/. The integrator is superior to competing designs in terms of all relevant metrics.
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This paper describes the implementation of a low-power, very long time constant integrator for use in an adaptive neural recording system for implantable neuroprostheses of very low frequency continuous-time filters. The integrator is based on the OTA-C approach and a very small transconductance (g/sub m/) of 125 pA/V was achieved by cascading a short chain of g/sub m/-1/g/sub m/ stages. The time constant of the integrator is tunable between 0.8 s to 2.5 s, and any offset voltages at the output terminal may be trimmed. The circuit was fabricated in a 0.8 /spl mu/m CMOS process, dissipates 230 nW from /spl plusmn/1.5 V power supplies (excluding the bias circuitry and output buffer) and has a core area of 0.1 mm/sup 2/. The integrator is superior to competing designs in terms of all relevant metrics.
Key concepts: Integrator, Op amp integrator, CMOS, Transconductance, Time constant, Passive integrator circuit, Offset (computer science), Voltage