2003•Unpublished venueRequires access

A standard cell set for delay insensitive VLSI design

Paolo Antognetti, P. Danielli, Alessandro De Gloria, Paolo Faraboschi, Matteo Oliveri

Open publisher page 5 citations

Abstract

Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complexity and speed parameters of each cell are reported. A first example of layout obtained by the system is present and evaluated.>

About this research paper

What this paper is about

Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complexity and speed parameters of each cell are reported. A first example of layout obtained by the system is present and evaluated.>

Why it matters

OpenAlex reports 5 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complexity and speed parameters of each cell are reported. A first example of layout obtained by the system is present and evaluated.>

Key concepts: Very-large-scale integration, Standard cell, Computer science, Set (abstract data type), Electronic circuit, Emphasis (telecommunications), Field (mathematics), Computer engineering

Related papers

Back to paper searchBrowse research topicsOriginal source
A standard cell set for delay insensitive VLSI design — Research Paper | ScholarLens