A standard cell set for delay insensitive VLSI design
Paolo Antognetti, P. Danielli, Alessandro De Gloria, Paolo Faraboschi, Matteo Oliveri
Abstract
Paolo Antognetti, P. Danielli, Alessandro De Gloria, Paolo Faraboschi, Matteo Oliveri
Abstract
Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complexity and speed parameters of each cell are reported. A first example of layout obtained by the system is present and evaluated.>
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Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complexity and speed parameters of each cell are reported. A first example of layout obtained by the system is present and evaluated.>
Key concepts: Very-large-scale integration, Standard cell, Computer science, Set (abstract data type), Electronic circuit, Emphasis (telecommunications), Field (mathematics), Computer engineering