A CAD tool for first hand CMOS circuit selection

For a given Boolean expression, various CMOS circuit implementations are possible. In this paper we describe a CAD tool that aids the designer towards optimum circuit selection with first hand information on delay, area and power consumption. The program reads in a function description from SIS in BLIF format. Using factoring technique, several versions of the function are derived then a multi-level logic synthesis and minimization algorithms map each function into a circuit topology. The tool then analyzes the performance of each circuit and finds the optimum circuit topology and transistor sizing according to the given criteria supplied as weights (constants) to the program.