Yield improvement of wafer-scale integrated systolic structures via redundancy

Some studies on the yield of integrated circuits have been done in the past, and several techniques to improve the yield of vlsi circuits via redundancy have been proposed. The objective of this work is to evaluate the concepts of local redundancy, intermediate redundancy, and temporal redundancy. Results obtained for local redundancy at the processing-element (PE) level show that the method probably is not of great interest for yield enhancement of large systolic arrays for wafer scale integration. Local redundancy within PEs can be useful if the increase in area of the resulting PE is not too great. The intermediate redundancy scheme deserves more investigation. Interconnection flexibility provided by this architecture coupled with redundant PEs results in improved yield by providing a simple communication structure which allows access to spares. 10 references.