Memory optimizations and exploration for embedded systems

The increase in level of abstraction of modern VLSI designs is accompanied by a corresponding increase in complexity of the building blocks that constitute the design library available to the tools used to automatically synthesise these designs from behavioral specifications. Modern design libraries frequently consist of pre-designed mega-cells such as embedded microprocessor cores and memories. The thesis aims at efficient utilization of memory-based modules such as Data Cache, Scratch-Pad Memory, and DRAM during System Synthesis. During System Synthesis, a behavioral specification could be realized in either hardware or software. In the case of hardware realization, CDFG restructuring techniques are proposed for exploiting efficient access modes of modern DRAMs in High-Level Synthesis. The case of a software realization by mapping a behavior into an embedded processor is characterized by several unique optimization opportunities that have not been addressed by general purpose compiler and architecture research. Applications involving large arrays typically store such data in off-chip DRAMs, with a small amount of on-chip memory, in the form of data cache and Scratch-Pad memory. We describe techniques for memory data organization in order to improve cache performance, followed by a technique for partitioning data between on-chip Scratch-Pad memory and off-chip memory with the objective of minimizing off-chip memory accesses. Finally, we outline a strategy for architectural exploration of on-chip data memory, consisting of appropriate sizing and parameterization of data cache and Scratch-Pad memory, that involves a rapid estimation of the expected performance for various memory configurations. This estimation can serve as an important feedback to the system designer, who can then select an appropriate memory structure for the synthesized behavior.* ftn*Originally published in DAI Vol. 58, No. 11. Reprinted here with corrected title.