A method of speculative dual-path execution for VLIW processors
Hiroyuki Shimajiri, T. Yoshida
Abstract
Hiroyuki Shimajiri, T. Yoshida
Abstract
VLIW processors are widely implemented in embedded computer systems that require low power consumption and small area. However, there is a major problem that VLIW processors execute many NOP operations while running a nonnumerical application. To solve this problem, we propose a new method of speculative multipath execution using a small and simple dynamic scheduling mechanism for VLIW processors. While speculatively executing, a VLIW processor applied our method merges both VLIW instructions of branch paths into one instruction by using NOP operations. It can simultaneously execute both paths by executing merged VLIW instructions. By applying our method to VLIW processors, they are able to reduce the number of executing NOP operations and to improve their performance. We compare IPCs of the VLIW processor applied our method and a VLIW processor applied the delayed branch method. Our simulation results on SPECint95 benchmarks show that our method can achieve from 18% to 33% and from 72% to 132% IPC improvement when the branch latency is one cycle and four cycles respectively.
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VLIW processors are widely implemented in embedded computer systems that require low power consumption and small area. However, there is a major problem that VLIW processors execute many NOP operations while running a nonnumerical application. To solve this problem, we propose a new method of speculative multipath execution using a small and simple dynamic scheduling mechanism for VLIW processors. While speculatively executing, a VLIW processor applied our method merges both VLIW instructions of branch paths into one instruction by using NOP operations. It can simultaneously execute both paths by executing merged VLIW instructions. By applying our method to VLIW processors, they are able to reduce the number of executing NOP operations and to improve their performance. We compare IPCs of the VLIW processor applied our method and a VLIW processor applied the delayed branch method. Our simulation results on SPECint95 benchmarks show that our method can achieve from 18% to 33% and from 72% to 132% IPC improvement when the branch latency is one cycle and four cycles respectively.
Key concepts: Very long instruction word, Computer science, Parallel computing, Embedded system