Study on electrical performance of stacking die package with silicon interposer

As one kind of effective integration structure, die stacking is widely used in advanced packaging designs, like System in Package (SiP), Chip Scale Package (CSP), Multi-Chip Module (MCM), etc. Conventional design of the stacking structure highly depends on parameters of the chip design, such as die size and bonding pad distribution. In this paper, stacking structure of a Processor Module package with silicon interposer has been designed. Electrical performance of different interconnection paths, mainly focused on output of the upper chip, was evaluated through electromagnetic simulation. Results showed that using silicon interposer can not only decrease failure risks of long wire bonding, but also improve electrical performance of interconnection in comparison to direct long bonding wire structures. Moreover, as partial interconnections are realized on interposer, routing space of package substrate would be increased, which helps to further reduce package size.