2004•ITC-CSCC :International Technical Conference on Circuits Systems, Computers and CommunicationsRequires access

A Pre-Synthesis Power Estimation Method for Behavioral Level VLSI Design

Kazuto Uehara, Hideo Araki, Toshiro Kutsuwa, Katsumi Harashima

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Key concepts: Very-large-scale integration, High-level synthesis, Estimation, Computer science, Power (physics), Reliability engineering, Engineering, Embedded system

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A Pre-Synthesis Power Estimation Method for Behavioral Level VLSI Design — Research Paper | ScholarLens