A High Performance Two-Level Register File Organization

Dynamic superscalar processors execute instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact on the size of this window as most in-flight instructions are assigned a new physical register. A large register file helps improve the instruction-level parallelism (ILP), but has a detrimental effect on clock speed, especially at future technologies. In this paper, we propose a two-level register file organization, where the first level only contains values that potentially have active consumers in the pipeline. The second level contains those values that are going to be used only in the event of a branch mispredict or an exception, and has minimal port requirements. Adding the second level shows overall speedups of 1.22, 1.06, and 1.19 relative to an architecture without a second-level cache for three different processor models for a varied benchmark set. A small first-level register file supported by a second-level register file can support as much ILP as a much larger single-level register file, thus having favorable implications for clock speed and power.