Rapid Prototyping of Hardware/Software Codesign for Embedded Signal Processing
Yin‐Tsung Hwang, Yuan-Hung Wang, Jer-Sho Hwang
Abstract
Yin‐Tsung Hwang, Yuan-Hung Wang, Jer-Sho Hwang
Abstract
In this paper, we propose a target board architecture suitable for embedded signal processing applications based on hardware software codesign. The target board, which serves as a system attached to a host PC via a PCI bus interface, contains a TMS320C30 DSP processor and up to four Xilinx XC5204 FPGAs. The software and hardware sections of the codesign can be easily implemented using C and VHDL programming in the C30 processor and FPGAs, respectively. Based on the proposed target board architecture, the interface circuitry and the communication protocols between the hardware (FPGAs) and software (C30) sections are first derived. The interface circuitry is described in VHDL code and will be added to the FPGA design for high level synthesis. Five types of HW/SW communications are supported. A HW/SW codesign flow is also exploited, and a partitioning verification procedure is developed. To illustrate the merits of the proposed system, a HW/SW codesign implementation example based on the G.728 LD-CELP decoder for speech compression is described.
OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
In this paper, we propose a target board architecture suitable for embedded signal processing applications based on hardware software codesign. The target board, which serves as a system attached to a host PC via a PCI bus interface, contains a TMS320C30 DSP processor and up to four Xilinx XC5204 FPGAs. The software and hardware sections of the codesign can be easily implemented using C and VHDL programming in the C30 processor and FPGAs, respectively. Based on the proposed target board architecture, the interface circuitry and the communication protocols between the hardware (FPGAs) and software (C30) sections are first derived. The interface circuitry is described in VHDL code and will be added to the FPGA design for high level synthesis. Five types of HW/SW communications are supported. A HW/SW codesign flow is also exploited, and a partitioning verification procedure is developed. To illustrate the merits of the proposed system, a HW/SW codesign implementation example based on the G.728 LD-CELP decoder for speech compression is described.
Key concepts: Computer science, VHDL, Field-programmable gate array, Embedded system, Computer hardware, Software, Digital signal processing, Interface (matter)