Design of a multiplier with low power data-compressors

A parallel structured 54/spl times/54 bit multiplier with low power data compressors is proposed. Using a tally-function circuit, an optimized low power data compressor is designed. The average power consumption of the proposed data compressor is reduced by about 35%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one.