Flexible memory: A novel main memory architecture with block-level memory compression

Main memory system is facing increasingly high pressure from the advances of multi-core processors. The simplicity of conventional memory architecture has helped minimize memory latency and reduce the design cost. However, in present multi-core era, it is increasingly attractive to adopt flexible and advanced memory organization to further improve memory bandwidth utilization, power efficiency, and reliability, despite an increase of memory system complexity. Motivated by the idea, we propose an innovative memory compression scheme with a flexible memory organization, used in combination with the recently proposed, power-efficient sub-ranked memory. Our detailed simulation show that the scheme may gain an average of 1.5× effective capacity gain, reduce the power consumption of memory subsystem by up to 45%, on average in the range from 13% to 16%, and yield moderate performance improvement.