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Synthesis for Testability: Binary Decision Diagrams

Bernd Becker

Open publisher page 35 citations

Abstract

We investigate the testability properties of Boolean circuits derived from (Reduced Ordered) Binary Decision Diagrams. It is shown that BDD-cirucits (or at least) BDD-like circuits are easily testable with respect to different fault models (cellular, stuck-at and path delay fault model). Furthermore the circuits and the test sets can be constructed efficiently.

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What this paper is about

We investigate the testability properties of Boolean circuits derived from (Reduced Ordered) Binary Decision Diagrams. It is shown that BDD-cirucits (or at least) BDD-like circuits are easily testable with respect to different fault models (cellular, stuck-at and path delay fault model). Furthermore the circuits and the test sets can be constructed efficiently.

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OpenAlex reports 35 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

We investigate the testability properties of Boolean circuits derived from (Reduced Ordered) Binary Decision Diagrams. It is shown that BDD-cirucits (or at least) BDD-like circuits are easily testable with respect to different fault models (cellular, stuck-at and path delay fault model). Furthermore the circuits and the test sets can be constructed efficiently.

Key concepts: Binary decision diagram, Testability, Boolean function, Computer science, Binary number, Algorithm, Fault (geology), Electronic circuit

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