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2002•Unpublished venueRequires access

VLSI design and implementation of analog CMOS 2/sup nd/ generation current conveyors

Somaya I. Kayed, Hani F. Ragaie, M. Abou El-Ela, Fouad A. S. Soliman

Open publisher page 2 citations

Abstract

In this paper we have designed and implemented a positive second generation enhanced current conveyor (CCII+) using a standard low-cost CMOS technology. The proposed circuit consists of CCII+ with two full integrated current sources. The proposed wide band CCII+ is shown to be realizable only with a high output impedance regulated feedback current source design. The fabricated chip (1.2 /spl mu/ CMOS) is tested, measured and verified with SPICE simulation.

About this research paper

What this paper is about

In this paper we have designed and implemented a positive second generation enhanced current conveyor (CCII+) using a standard low-cost CMOS technology. The proposed circuit consists of CCII+ with two full integrated current sources. The proposed wide band CCII+ is shown to be realizable only with a high output impedance regulated feedback current source design. The fabricated chip (1.2 /spl mu/ CMOS) is tested, measured and verified with SPICE simulation.

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OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

In this paper we have designed and implemented a positive second generation enhanced current conveyor (CCII+) using a standard low-cost CMOS technology. The proposed circuit consists of CCII+ with two full integrated current sources. The proposed wide band CCII+ is shown to be realizable only with a high output impedance regulated feedback current source design. The fabricated chip (1.2 /spl mu/ CMOS) is tested, measured and verified with SPICE simulation.

Key concepts: Current conveyor, CMOS, Spice, Electronic engineering, Electrical impedance, Very-large-scale integration, Current (fluid), Electrical engineering

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