Analysis of the trade-off between bandwidth, resolution, and power in ΔΣ analog to digital converters

The trade-off relationship between bandwidth, resolution, and power in /spl Delta//spl Sigma/ ADCs realized in CMOS technologies is studied. The design of /spl Delta//spl Sigma/ converters is discussed in order to achieve an optimum trade-off between bandwidth, resolution, and power, or alternatively the maximum bandwidth, resolution product. A best case estimation of this trade-off is derived and compared with the known limits imposed by noise and matching. It is shown that the fundamental limit imposed by noise, when circuit considerations are taken into account, becomes comparable to the matching limit in current technologies. Therefore, even if the matching characteristics of technologies improve, the bandwidth, resolution, and power trade-off of conventional /spl Delta//spl Sigma/ converters will not improve significantly.