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Inverter-based models for current analysis of CMOS logic circuits

A. Nabavi-Lishi, Nicholas C. Rumin

Open publisher page 2 citations

Abstract

This paper presents techniques for reducing CMOS gates to equivalent inverters for current and delay analysis. These do not assume a single input switching, and they account for the speed of the input transitions, as well as for the relative positions of the inputs in series-connected MOSFETs. The resulting inverters have been tested using previously published current analysis techniques. The gate reduction time is small compared to that for determining the current, and there is no significant effect on the accuracy.>

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What this paper is about

This paper presents techniques for reducing CMOS gates to equivalent inverters for current and delay analysis. These do not assume a single input switching, and they account for the speed of the input transitions, as well as for the relative positions of the inputs in series-connected MOSFETs. The resulting inverters have been tested using previously published current analysis techniques. The gate reduction time is small compared to that for determining the current, and there is no significant effect on the accuracy.>

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OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper presents techniques for reducing CMOS gates to equivalent inverters for current and delay analysis. These do not assume a single input switching, and they account for the speed of the input transitions, as well as for the relative positions of the inputs in series-connected MOSFETs. The resulting inverters have been tested using previously published current analysis techniques. The gate reduction time is small compared to that for determining the current, and there is no significant effect on the accuracy.>

Key concepts: CMOS, Inverter, Electronic engineering, Electronic circuit, Logic gate, Computer science, Current (fluid), Electrical engineering

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