1993•European Solid-State Circuits ConferenceRequires access
Fully Digital Redundant Random Number Generator in CMOS Technology
Antonio J. Acosta, M.J. Bellido, M. Valencia, A. Barriga, J.L. Huertas
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Abstract
This communication presents a new fully-digital redundant Random Number Generator. Its structure is that of a standard LFSR, with the difference that it includes one 1-bit ros-RNG in each basic cell. The design is modular, provides reasonable performances - simplicity, low cost and high speed -, it generates truly random sequences (i.e. aperiodic and unpredictable) and allows choosing random or pseudorandom sequences. Working like a truly random generator, the circuit produces random sequences from the first clock cycle, i.e., user must not wait a latency time to obtain a good sequence.