Implementation of ladder diagram for programmable controller using FPGA

Sequential control is an elementary technology for manufacturing systems. Manufacturing devices or systems are usually controlled by programmable controllers (PCs). In order to satisfy the requirements of downsizing and hidden information, we develop a novel type of controller which is implemented using the field programmable gate array (FPGA) as an application specific integrated circuit (ASIC). The widely used programming language in the area of sequential control, Ladder Diagram (LD), is also implemented on such a FPGA. The main bottleneck of the implementation is how to realize cyclic scan, which is the most significant characteristic of PCs. We describe two methods to implement the cyclic scan. One involves using the clock event of the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), and the other is of translating a coil as a self-hold circuit of LD into an appropriate flip-flop element of VHDL. We also compare the two methods and show the benefits of the new controller implemented by FPGA.