2010•European Microwave Integrated Circuits ConferenceRequires access
Distributed modeling of layout parasitics effects in CMOS power devices
Doris A. Chan, M. Feng
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Abstract
The effects of distributed power device model optimization and extraction techniques are incorporated to predict the f T , f max , transducer power gain and output power in 130 nm CMOS. Small signal and large signal of BSEVI-RF model, ICF-D1 model, and measured power device results are compared for model verification.