2006Unpublished venueRequires access

Wide Capture Range PLL with LC-VCO

Xuecheng Zou, Xiangqian Jiang, Dingzhong Xiao, Sanqing Liu

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Abstract

A wide capture range PLL with low phase noise is proposed and analyzed. The PLL incorporates a LC voltage-controlled oscillator (VCO) to get low phase noise while the divider is controlled by low pass filter (LPF) voltage to achieve wide capture range. The proposed PLL is designed based on the SMIC 0.18-/spl mu/m 1P5M CMOS process with a 2.5 V supply voltage. HSPICE simulation shows that the output frequency of proposed PLL alternates from 0.3 GHz to 1.4 GHz, and the phase noise is below-120 dB at a 300 KHz offset from VCO center frequency.

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What this paper is about

A wide capture range PLL with low phase noise is proposed and analyzed. The PLL incorporates a LC voltage-controlled oscillator (VCO) to get low phase noise while the divider is controlled by low pass filter (LPF) voltage to achieve wide capture range. The proposed PLL is designed based on the SMIC 0.18-/spl mu/m 1P5M CMOS process with a 2.5 V supply voltage. HSPICE simulation shows that the output frequency of proposed PLL alternates from 0.3 GHz to 1.4 GHz, and the phase noise is below-120 dB at a 300 KHz offset from VCO center frequency.

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Available abstract

A wide capture range PLL with low phase noise is proposed and analyzed. The PLL incorporates a LC voltage-controlled oscillator (VCO) to get low phase noise while the divider is controlled by low pass filter (LPF) voltage to achieve wide capture range. The proposed PLL is designed based on the SMIC 0.18-/spl mu/m 1P5M CMOS process with a 2.5 V supply voltage. HSPICE simulation shows that the output frequency of proposed PLL alternates from 0.3 GHz to 1.4 GHz, and the phase noise is below-120 dB at a 300 KHz offset from VCO center frequency.

Key concepts: Voltage-controlled oscillator, Phase-locked loop, Phase noise, PLL multibit, CMOS, Voltage, Electronic engineering, Offset (computer science)

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