Design and implementation of high performance architecture for packet classification

Packet Classification is a core function used in an internet router, firewall, network security and quality of services. A flow of packets is decided by the header fields of incoming packets. Software solutions for packet classification are not suitable for wire-speed processing and are not secure. For wirespeed and secure network access, hardware solutions for packet classification are mandatory which can also sustain high throughput at low latency. Memory required for hardware architecture is also a crucial problem. In this paper, we have performed classification of packets using basic XNOR gate. We compare our proposed design with StrideBV which is one of efficient decomposition based technique for packet classification. The results obtained by synthesis and stimulation using XilinxISE Design tool 13.1 are presented in this paper. From the results, we have concluded that our proposed technique is memory efficient as well as has low latency than StrideBV.