Beyond logic synthesis

Synthesis is the enabling technology and foundation of High-Level Design (HLD), the third generation of Electronic Design Automation (EDA). In simple terms, synthesis uses a functional specification and user constraints to automatically generate an optimized gate-level description. The more complete the synthesis tool, the more it takes care of implementation details, leaving designers to more quickly add value at higher levels of abstraction. While synthesis really began as logic optimization, hence the name "logic synthesis", Synopsys provides capabilities far beyond the scope of logic optimization. Today these include RTL synthesis, architectural synthesis, and floorplan management. Synopsys is also exploring multiple-cycle optimization which can move the designer to a behavioral level of abstraction. The remainder of this document describes the various types of synthesis, their requirements, and their value to a designer.