Design and performance analysis of an asynchronous pipelined multiplier with comparison to synchronous implementation

Synchronous techniques have dominated digital logic system design for decades because they are well understood and less complicated to implement. With the advent of more exotic high-speed transistors, the issues of clock skew, system performance, power consumption, and technology migration become critical to synchronous system designers. Asynchronous digital design techniques utilize a local completion signal or request(acknowledge handshake to lend the stability afforded by the global clock in synchronous systems. This research evaluates a moderately complex digital system, an 8x8-bit multiplier utilizing high speed Indium Phosphide heterostructure bipolar junction transistors, to determine whether asynchronous logic design can compete with synchronous design in terms of system speed and power consumption. Theoretical timing equations are developed that relate the relative merits of each technique for input-to- output latency and system throughput. Tanner SPICE simulation tools are used to evaluate the full 8x8-bit asynchronous array multiplier. Finally, direct comparisons are made between five separate pipelined configurations of the multiplier utilizing both synchronous and asynchronous timing methodologies. As integrated circuits become smaller, faster, and more complex, asynchronous schemes will continue to mature and become more prevalent in digital system design.