Mitigating Limited PCM Write Bandwidth and Endurance in Hybrid Memory Systems

With the rise of big data and cloud computing, there is increasing demand on memory capacity to solve problems of large sizes and consolidate computation tasks. For large capacity memory systems, DRAM is a significant source of energy consumption. Non-volatile memory, such as Phase-Change Memory (PCM), is a promising technology for constructing energy-efficient memory. Unlike DRAM, PCM has negligible background (static) power and allows high density packaging. But PCM also has limited write bandwidth and write endurance. Hybrid memory systems have been proposed to combine the high-density and low standby power of PCM with the good write performance of DRAM. This thesis addresses two challenges which are unique to hybrid memory systems. The first challenge is the limited PCM bandwidth, which can become a performance bottleneck. The second challenge is the non-contiguous physical memory due to retired memory pages. Since PCM cells have limited write endurance, it is inevitable to gradually have increased number of uncorrectable errors during the lifetime. Memory pages that have detected errors are normally retired by the OS, which create unusable “holes” in the physical memory. These unusable holes make it difficult to construct traditional superpages, which can incur significant performance overhead. In this thesis, I propose three solutions to address these two challenges. First, I observed that an unbalanced distribution of modified data bits among PCM chips significantly increases PCM write time and hurts effective write bandwidth. I propose new XOR-based mapping schemes between program data bits and PCM cells to improve PCM write throughput by spreading modified data bits evenly among PCM chips. Second, I propose a compressed DRAM cache scheme to improve DRAM effective capacity and reduce write traffic to PCM. A new adaptive delta-compression technique for modified data is used to achieve a large compression ratio. Third, I propose Gap-tolerant Sequential Mapping, a new memory page mapping scheme, to construct superpages from non-contiguous physical memory. The proposed three solutions have simple and practical designs, and can be easily adopted in future hybrid memory systems.