A performance model for network processor architectures in packet processing system

Network processors (NPs) are designed to provide both performance and flexibility through the implementation of both parallel and programmable architectures. Typically, such processors encompass a parallel processor core with several memories and specialized co-processors. A common task performed by such processors is packet processing that is both complex and highly repetitive. Consequently, the challenge is to define an on-chip network processor architecture that is capable of meeting the performance requirements of packet processing. With the current technological advances, it is expected that many (network) processor cores are to be incorporated onto the same chip to perform packet processing for which an efficient configuration must be determined. In this paper, we propose a general framework for analyzing the performance of a network processor that consists of an (on-chip) network of NPs. For this purpose, we utilize queuing theory to model the proposed network processor and analyze it. More specifically, the Jackson network model is utilized to represent our network processor. The simulation results show that the proposed network processor is able to improve the response time and throughput when compared to a more traditional network processor.